This invention relates to a semiconductor integrated circuit, and more specifically to an improvement in the circuit pattern design of logic LSIs base on so-called standard cell methodology.
Recent fine patterning technology for semiconductor circuits makes it possible to provide logic LSIs having numbers of gates ranging from a few to tens of thousands of gates per chip. On the other hand, there are increasing demands for a variety of logic LSIs tailored to meet user's specific requirements.
The provision of a fully-customized LSI necessarily starts with the design and positioning of transistors on a chip, and design optimization is directed to maximizing the efficiency in chip area utilization and performance of the circuit. However, such full custom design has disadvantages in that a long turnaround time (one-half year or more) is generally required, and there is little flexibility in the modification of the chip design because it has been highly optimized. As a result, several methodologies, such as gate array and standard cell methods, have been proposed for developing customized LSIs in a short turnaround time and with design flexibility.
In the gate array method, a customized logic LSI is fabricated by only providing wirings for a desired circuit network on a silicon wafer in stock, on which transistors are formed in advance. The number of masks necessary for the customization is about 1/3 of the total number of masks used in the fabrication of the LSI.
The standard cell method uses pre-defined patterns of unit circuits (cells) corresponding to logic gates (e.g., NAND, NOR, inverter, flip-flop, etc.). These patterns of the cells are registered as a library in a computer system. The design of an LSI chip is carried out on the basis of the placement and interconnection routing of the cells with the support of a CAD (computer aided design) system, and all the masks are customized for each kind of LSI.
The standard cell method has the following features: (a) the information on the patterns and electrical characteristics of circuit elements such as transistors is well-organized in the library of the CAD system, so that efficient control of LSI chip design can be attained; (b) as a result of (a), errors which usually occur in the chip design can be decreased; (c) more efficient use of chip area can be achieved than in the gate array method. Thus, the standard cell method has a relatively large amount of freedom in the chip design, provides a possibility of LSI design without expert knowledge of the circuit elements, and decreases the risks involved in the development of the LSI.
FIG. 1 is a conceptual schematic diagram of an example of the placement and interconnection-routing of cells in accordance with the standard cell method. Referring to FIG. 1, various kinds of cells 1 are arranged in rows on a semiconductor substrate 2. They are formed in a substantially rectangular frame of the same height but generally vary in width in accordance with the kind of cell. These cells are interconnected by wirings 3 formed to be distributed in the regions (sometimes referred to as wiring channels) between adjacent sets of two cell rows. Each of the cells 1 has a predefined pattern for providing circuit elements such as transistors and inner wiring layers therein. FIG. 2A is a plan view of an exemplary pattern providing a 2-input NAND gate of CMOS (complementary metal oxide semiconductor) type logic in a frame, and having the equivalent circuit shown in the circuit diagram of FIG. 2B.
Referring to FIG. 2A, the 2-input NAND cell occupies an area defined by a substantially rectangular virtual frame indicated by broken line 100. The dimension of the frame size is in the range of about a few tens of microns to one hundred microns. Circuit components, such as MOS transistors P1, P2, N1 and N2, are formed in the frame, while nodes for the external connections are formed to extend across the frame 100. The hatched areas illustrate wiring layers of aluminum (A1), for example. I1 and I2 indicate the nodes for receiving input signals and OT represents an output node. B.sub.VDD and B.sub.VSS are the bus lines to be connected to positive and negative side voltage sources V.sub.DD and V.sub.SS, respectively.
For a better understanding of FIG. 2A, the configuration of the pattern shown in FIG. 2A is further explained with reference to FIGS. 2C and 2D. FIG. 2C is a plan view of a bulk pattern providing the MOS transistors P1, P2, N1 and N2, and FIG. 2D is a plan view of the pattern of inner wiring layers interconnecting the transistors, including the layers for the bus lines B.sub.VDD and B.sub.VSS. Referring to FIG. 2C, a p-type region 101 (enclosed by solid line 101') and an n-type region 102 (enclosed by solid line 102') are formed in the frame 100 by selectively implanting p-type and n-type impurities therein. The area outside the regions 101 and 102 are coated with a thick insulating layer (not shown), for example, an oxide layer (generally referred to as a "field oxide layer"). A pair of gate electrodes 103 and 104, both composed of polysilicon, for example, are formed across the p-type and n-type regions 101 and 102 with the intervention of respective thin insulating layers (not shown), such as oxide layers (generally referred to as "gate oxide layers"), formed on the regions 101 and 102. Thus, p-channel MOS transistors P1 and P2 are formed in the n-type region 101 and n-channel MOS transistors N1 and N2 are formed in the p-type region. The p-type region 101 and n-type region 102 are respectively provided with extra regions 109 and 110 which are referred to as bus line contact regions hereinafter, and respective contacts to the bus lines B.sub.VDD and B.sub.VSS are formed therein as described below.
A set of wiring patterns 105, 106 and 107, as shown in FIG. 2D, are fabricated on the bulk pattern of FIG. 2C, and are composed of aluminum, for example. The wiring patterns have contacts to the bulk pattern through windows 108 formed in the insulating layer (not shown) at the positions indicated in FIGS. 2A and 2D. Thus, the p-channel transistors P1 and P2 and n-channel transistors N1 and N2 are interconnected to form a 2-input NAND gate as shown in FIG. 2B. On the extended portions 105' and 107' in the vertical direction of the bus lines B.sub.VDD and B.sub.VSS are provided contact points to the corresponding underlying portions of the p-type and n-type regions (aforesaid bus line contact regions 109 and 110) to supply the portions with positive and ground potential, respectively. The regions occupied by such extended portions 105' and 107' of the bus lines and their coresponding underlying p-type and n-type portions are referred to as bus line contact regions. The configurations of other logic cells including a NAND gate having 3 or 4 inputs, a NOR gate, an inverter, etc. are essentially the same as explained with reference to FIGS. 2C and 2D.
For generating a final bulk pattern of a logic circuit cell as shown in FIG. 2A, individual mask patterns for each of the processes (for example, those for creating p-type and n-type regions, gate electrodes, wiring lines, etc.) are designed. A complete set of information relevant to the mask patterns for each kind of cell, is registered in a library of a CAD system. In LSI chip design, therefore, when a designer has access to the library by using the name of a desired cell, the frame of the cell is displayed on a display device. The designer is only required to determine the location of the cell frame and the routing of interconnections among the cells. The pattern information for all of the cells disposed on a chip is edited and stored in a mask pattern data file. Then, a comprehensive mask pattern for each production process relevant to all of the cells, is generated by a computer system.
FIG. 3A is a plan view of a partial bulk pattern of a CMOS-LSI, showing a 3-input NAND gate (Cell 1) and 4-input NAND gate (Cell 2) abutting each other, together with internal wiring layers (hatched patterns) formed thereon, positioned according to conventional standard cell placement rules. FIGS. 3B and 3C are circuit diagrams of the equivalent circuits of the 3-input NAND gate and the 4-input NAND gate, respectively, in FIG. 3A. Referring to FIG. 3A, Cells 1 and 2 are defined in the respective virtual frames denoted by reference numbers 200 and 300. Cell 1 includes a p-type region 201, an n-type region 202 and three gate electrodes 203, all for providing p-channel transistors P1, P2 and P3 and n-channel transistors N1, N2 and N3. Cell 2 includes a p-type region 301, and n-type region 302 and four gate electrodes 303, all for providing p-channel transistors P1, P2, P3 and P4 and n-channel transistors N1, N2, N3 and N4. The transistors in Cells 1 and 2 are interconnected by respective first and second sets of internal wiring layers, wherein wiring layers 205, 206, 207 form the first set, and wiring layers 305, 306, 307 form the second set. Thus, a 3-input NAND gate and a 4-input NAND gate are provided in the frames 200 and 300, respectively. The wiring layers 205 and 305 are connected to each other with their nodes extending out across the frames 200 and 300, respectively, and the wiring layers 207 and 307 are connected to each other with their nodes extending out across the frames 200 and 300, respectively, so that the respective bus lines B.sub.VDD and B.sub.VSS can run throughout the cells in the row.
The pattern information for all the cells placed on the same chip is processed in a CAD system, and an individual mask pattern for each fabrication process is generated in common for all of the cells. Such mask patterns include those for: (a) defining regions to be later characterized as the p-type and n-type regions; (b) providing mask layers for the regions to which p-type and n-type impurities are to be selectively diffused; and (c) delineating the gate electrodes and the wiring layers.
As described above, in the conventional standard cell method, the adjoining cells are disposed to have frames which are abutting but not overlapping each other, and effective use of chip area is limited by the adjustment in cell placement which is necessary to minimize the region allocated for the aforesaid wiring channels. Even if the wiring channel area is minimized, the efficiency in the use of chip area in the conventional standard cell method is, in general, far from the efficiency for the fully customized chip. Therefore, the improvement of chip area utilization has been a matter of serious concern with the conventional standard cell methodology.